The present invention relates to a technology effective for application to a method of testing, designing and manufacturing a semiconductor integrated circuit like a logic integrated circuit, and to a technology effective for application to a so-called system LSI (Large-Scale Integration) wherein, for example, a custom logic circuit having a function desired by a user is added to a one-chip microcomputer.
In a logic LSI, a so-called scan path system for serially connecting flip-flops constituting an internal sequence circuit, and inputting test patterns to thereby test whether the logic of an internal circuit is normal, has been adopted for the purpose of a test on the internal circuit. In recent years, a logic LSI with a BIST (Built-In Self-Test) system provided thereinside with a test circuit for generating test patterns has also been provided as an alternative to the scan path system.
In addition to the drawback that since the test patterns are serially inputted, a test time interval increases upon the examination of the scan path system, a problem arises in that as the logic scale of an LSI increases as in recent years, the number of test patterns for enhancing defect detection increases exponentially, thereby incurring an increase in the load on a tester for generating test patterns and a great rise in the cost of the tester, and the cost per chip also increases because the time required to test one LSI also increases.
On the other hand, since a random pattern generator is used to form test patterns, it is hard to say that the sufficient rate of defect detection is assured upon the BIST system test. Further, since it is connected to a tester to issue instructions upon the test, the load on the tester produces the need for an expensive tester during at least a test process, so that cost performance cannot be enhanced sufficiently. An LSI equipped with a BIST circuit has a problem in that a chip size increases by the BIST circuit itself and the cost rises, and yields are reduced due to the occurrence of a defect by the BIST circuit per se.
An object of the present invention is to provide a semiconductor integrated circuit wherein a self-examining test circuit can be configured without an increase in chip size.
Another object of the present invention is to provide the technology of manufacturing a semiconductor integrated circuit capable of testing an internal circuit without having to use an expensive tester.
A further object of the present invention is to provide the technology of designing a semiconductor integrated circuit which does not cause a reduction in yield due to the occurrence of a defect by the circuit per se.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present applications will be explained as follows:
A semiconductor integrated circuit according to the present invention is one wherein a plurality of programmable logic cells having storage elements and each capable of outputting an arbitrary logic output corresponding to an input according to information stored in each storage element are provided in areas other than circuit blocks on a semiconductor chip so as to spread over the semiconductor chip without space, for example, or one wherein a first programmable logic unit and a second programmable logic unit which respectively comprise a plurality of programmable logic cells having storage elements and each capable of outputting an arbitrary logic output corresponding to an input according to information stored in each storage element, are placed so as to interpose circuit blocks placed on a semiconductor chip therebetween, and the first programmable logic unit and the second programmable logic unit are capable of accessing in parallel.
In a logic LSI like a system LSI configured under a CBIC (Cell Base IC) system by an arrangement of macrocells such as a CPU core, a RAM, etc., free spaces have heretofore been defined between respective circuit blocks. The total amount thereof reaches 5 to 10% of a chip even on the average and might reach near 20% in the worst case. Converting it to the number of logic gates could yield the creation of gates approximates to four thousand to one hundred thousand in number. Therefore, since a test circuit for examining each in-chip circuit block can be configured using each of programmable logic cells provided in such free spaces, according to the above means, a self-examining test circuit can be formed without an increase in chip size, and a semiconductor integrated circuit capable of performing a non-defective product decision without using an expensive tester can be implemented. Since the test circuit is provided inside the chip, a circuit block to be tested is directly tested without being via other circuit blocks, and even a local circuit lying inside the circuit block can directly be tested. It is also possible to effect a sufficient test on an on-chip CPU or the like which have heretofore encountered difficulties in executing the sufficient test.
Preferably, a decoder circuit capable of selecting any of the plurality of programmable logic cells, and amplifier circuits each of which writes and reads information into and from each storage element in the programmable logic cell selected by the decoder circuit, are placed at a peripheral edge portion of the semiconductor chip. Thus, an arbitrary logic circuit can be added after the use of internal programmable logic cells in each of individual chip units.
Further, preferably, the programmable logic cell constitutes a test circuit for examining at least one of the circuit blocks. Thus, a test circuit is constructed by use of internal programmable logic cells in each of individual chip units to thereby make it possible to test the circuit blocks.
The programmable logic cell may preferably constitute a memory circuit accessible by any of the circuit blocks. Thus, the overhead of the circuit can be reduced, the chip size can be reduced, and the storage capacity of the entire on-chip system can be increased.
The programmable logic cell may preferably constitute a repairing circuit for mending a faulty portion which exists in any of the circuit blocks. It is thus possible to improve the yield of the chip.
Further, the programmable logic cell may preferably comprise a plurality of programmable logic units which respectively have 2n memory cells alternatively selected according to combinations of n sets (where n is a positive integer) with signals respectively set to positive-phase and a negative-phase and which are respectively configured so as to output the positive-phase and negative-phase signals according to data stored in each selected memory cell, variable wiring means provided with a plurality of signal lines for allowing connections to other programmable logic units, and switch elements capable of connecting or cutting off between the signal lines which intersect each other, and a wiring connection state storage unit which stores the state of each switch element of the variable wiring means therein. Owing to the setting of the input and output of each programmable logic circuit as differential signals, a noise-resistant semiconductor integrated circuit can be implemented even when the circuit is lowered in voltage.
A method of designing a semiconductor integrated circuit, according to the present invention is one which comprises the steps of, upon DA (Design Automation)-based design, laying out a plurality of programmable logic cells having storage elements and each capable of outputting an arbitrary logic output corresponding to an input according to information stored in each storage element so as to spread over the entire semiconductor chip, thereafter determining the layout of each of circuit blocks each having a desired function, and laying out each of the circuit blocks in a layout-determined area on the chip with its replacement by the programmable logic cell.
According to the above-described means, the layout of the circuit blocks each having the desired function can be determined in exactly the same manner as conventional without bearing the pre-laid out programmable logic cells in mind. Further, a test circuit for examining each in-chip circuit block can be configured by use of the programmable logic cell left between the laid-out circuit blocks. Therefore, a semiconductor integrated circuit wherein a self-examining test circuit can be configured, can be obtained without an increase in chip size.
A method of manufacturing a semiconductor integrated circuit, according to the present invention is one which comprises the steps of laying out a plurality of programmable logic cells having storage elements and each capable of outputting an arbitrary logic output corresponding to an input according to information stored in each storage element so as to spread over the entire semiconductor chip, thereafter determining the layout of each of circuit blocks each having a desired function, laying out each of the circuit blocks in a layout-determined area on the chip with its replacement by the programmable logic cell to thereby form the semiconductor integrated circuit, thereafter examining the programmable logic cells, forming a test circuit for checking at least one of the circuit blocks by using the programmable logic cell judged to be normal, and examining each circuit block by the test circuit to thereby remove a defective product.
According to the above-described means, the programmable logic cells left between the laid-out circuit blocks are examined. The test circuit for examining each of the circuit blocks is configured by use of the cell judged to be normal and performs testing. Therefore, a semiconductor integrated circuit in which a self-examining test circuit can be configured, can be implemented without an increase in chip size. Further, no yield is reduced due to the occurrence of a failure in the test circuit.
Further, after the examination of the circuit blocks by the test circuit configured by the programmable logic cell has been completed, a semiconductor integrated circuit judged to be defective, based on the result of examination is removed. The programmable logic cell having constituted the test circuit may have a make up of a logic circuit like a custom logic circuit having a function desired by a user. Thus, a semiconductor integrated circuit low in overhead can be implemented. After the examination of the circuit blocks by the test circuit has been finished, a portion having a defect detected by the examination may be repaired by the programmable logic cell having constituted the test circuit or by the programmable logic cell other than the same. Thus, since an LSI, which has heretofore been removed as a defective product, can be regarded as a non-defective product, the yield of the LSI can be enhanced.